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Vox Team ©2016 Radioactive The Way It Is All rights reserved. ABOUT RADIOSSREVIEW RadiosReview.com is a leading provider of radio review, covering consumer electronics, computer software, music, books and DVDs. The site also reviews tech accessories. Be sure to check out our other sites as well: All products recommended by RadiosReview.com are selected by our editorial team, independent of commercial relationships. At RadiosReview.com, we welcome innovation from outside sources. If your submission works, we will consider it. More information. Send form if you want to suggest a tech product for a future review.It will be appreciated that we are faced with the dilemma of the first network modem to support both TDMA and ATDMA in combination with the fixed modulation format of 16 kbps V.90. A combined TDMA/ATDMA network modem may employ two different data channels. One channel will carry data of a user and the other will carry the TDMA/ATDMA control information. The two channels could be controlled by the same logic and data decoding circuit or by separate logic and decoding circuits. Either way the two channels are preferably driven by the same clock. The clock is needed to control the two channels since each channel requires a different clock for synchronization. In the prior art the basic system clock is divided by 4 to produce the clocks for the TDMA and ATDMA channel. This implementation is simple and will function well when the clock frequency is 400 Hz or 1200 Hz. However when the V.90 modem clock rate is 2400 Hz (a 384 Hz clock) then the 2:1 clock divider produces 960 Hz and the two channels are no longer synchronized. This is particularly a problem with the digital signal processing or DSP circuitry which is normally set to operate at 384 Hz. In U.S. Pat. No. 5,477,258 to Fenton a V.90 modem with TDMA/ATDMA functionality is disclosed. Fenton's patent describes an interface between the TDMA and ATDMA networks which includes two different frequencies. The interface is synchronized by a clock which is a 1:1 frequency multiple of the TDMA and ATDMA clocks. This synchronization is achieved by using a shift register which delays by one clock period. The maximum data rate which Fenton can achieve in a TDMA environment is dependent upon the clock rate

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